The present invention is generally directed to electronic design automation (EDA) for creating integrated circuit products, such as, for example, system on chip (SOC) integrated circuit (IC) products and the like. More specifically, the present invention is directed to providing expeditious timing signoff verification and correction with minimal fixing during signoff of a physical circuit design.
While signoff systems and methods are known, such heretofore known systems and methods are encumbered by numerous deficiencies, not the least of which are required repeated transformative iterations between timing signoff and physical implementation, highly divergent timing analysis between timing signoff and physical implementation optimizers—with highly pessimistic timing characteristics and attendant false-positive violations (requiring over-fixing), inordinate turn around time, and overly burdensome storage, processing, and memory requirements. Such deficiencies have heretofore hindered efforts to minimize fabricated circuit product cost, time to market, power requirements, and substrate area while maximizing performance.
There is therefore a need for a system and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce over-fixing via remedial physical corrections of the circuit design for detected false-positive violations in the circuit design.